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Comment on Aside from being an open standard, what other benefits are there to RISC-V over x86/ARM?

While true, RISC-V probably isn’t the architecture for that. Better to use an old architecture whose patents have expired, and implement it on a new, smaller process.

RISC-V is good as an alternative to ARMv8 where the use case doesn’t quite fit what ARM is doing — or to implement in a country where there may be restrictions on how ARM is sold/deployed.

What I’m waiting for is for someone to implement something in RISC-V similar to Apple’s ARM implementation, with all the cores and memory on a single die. No need to do FPGA when you can just fab an unencumbered design in small batches for relatively cheap.

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litchralee@sh.itjust.works ⁨1⁩ ⁨day⁩ ago

Better to use an old architecture whose patents have expired, and implement it on a new, smaller process.

I’m not aware of any examples of an old architecture that was largely reused while ported to a new process, without requiring extensive redesigning of the analog components. Old processor architectures are a product of their day, making assumptions and decisions about the silicon paths that would be wholly invalidated if brought as-is to more-modern processes. It is nowhere near as simple as a copy/paste job of SystemVerilog or RTL.

To invest even one hour of design time to update, say, the 1970s Intel 4004 design (10 micrometer process) into the 2000s (130 nm) would be more expensive than just using RISC-V for free, which has already been fabricated using 22 nm, among other processes.

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- adespoton@lemmy.ca ⁨1⁩ ⁨day⁩ ago
  The MC68000, for example, is over 40 years old and out of patent. It’s been repackaged on a smaller process as the 68SEC000, and there are Verilog implementations available too.
  
  And that’s just the example that’s top of mind. There’s a whole line of low frequency Atmel processors too, but those are still very much in patent and so mostly tangential to this conversation.
  
  RISC-V doesn’t really make sense for simpler implementations though; you’d still have to do a bunch of work to simplify it, AND end up with an architecture very few are currently familiar with.
  
  Once Chinese implementations of RISC-V become endemic and there are enough people familiar with the architecture, it might make sense to start creating custom subsets on simplified processes. But we’re still years away from that.
  
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