Comment on Raspberry Pi is now a public company

• sleepybisexual@beehaw.org ⁨6⁩ ⁨months⁩ ago

  Hope that happens, maybe my riscv potato might get some use

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  • demesisx@infosec.pub ⁨6⁩ ⁨months⁩ ago

    Amen. I’d love to see Home Assistant start using it. I’m not holding out hope, though, because the guy behind Home Assistant is actively hostile.

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    • sleepybisexual@beehaw.org ⁨6⁩ ⁨months⁩ ago

      I have a uconsole r01

      I wanna be able to use it. Its borderline unuaaible rn

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      • demesisx@infosec.pub ⁨6⁩ ⁨months⁩ ago

        Much like the fediverse, we’re very early on that technology. We’re waiting for the network effect to take hold in both areas. Once it does, things will improve significantly, IMO.

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• perishthethought@lemm.ee ⁨6⁩ ⁨months⁩ ago

  I’m not familiar. Any recommendations?

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  • demesisx@infosec.pub ⁨6⁩ ⁨months⁩ ago

    hackaday.com/…/the-future-of-risc-v-and-the-visio…

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    • perishthethought@lemm.ee ⁨6⁩ ⁨months⁩ ago

      Super helpful, thank you! But maybe I missed one point: why is Arm bad or RiscV better? Why should we encourage Risc cpus?

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      • demesisx@infosec.pub ⁨6⁩ ⁨months⁩ ago

        RISC-V is an open instruction set, which should be what the Pi foundation (if their open source mission is to be taken at face value) would be switching to if they weren’t just a way for Broadcom to push their chips on the maker community under the guise of open source.

        riscv.org/…/what-is-risc-v-and-why-is-it-importan….

        RISC-V, an open-source instruction set architecture (ISA), has been making waves in the world of computer architecture. “RISC-V” stands for Reduced Instruction Set Computing (RISC) and the “V” represents the fifth version of the RISC architecture. Unlike proprietary architectures such as ARM and x86, RISC-V is an open standard, allowing anyone to implement it without the need for licensing fees. This openness has led to a surge in interest and adoption across various industries, making RISC-V a key player in the evolving landscape of computing. At its core, an instruction set architecture defines the interface between software and hardware, dictating how a processor executes instructions. RISC-V follows the principles of RISC, emphasizing simplicity and efficiency in instruction execution. This simplicity facilitates easier chip design, reduces complexity, and allows for more straightforward optimization of hardware and software interactions. This stands in contrast to Complex Instruction Set Computing (CISC) architectures, which have more elaborate and versatile instructions, often resulting in more complex hardware designs. The open nature of RISC-V is one of its most significant strengths. The ISA is maintained by the RISC-V Foundation, a non-profit organization that oversees its development and evolution. The RISC-V Foundation owns, maintains, and publishes the RISC-V Instruction Set Architecture (ISA), an open standard for processor design. The RISC-V Foundation was founded in 2015 and comprises more than 200 members from various sectors of the industry and academia.

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